Japanese Patent Application No. 2001-261778 filed on Aug. 30, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a non-volatile semiconductor memory device including memory cells each of which has two non-volatile memory elements controlled by one word gate and two control gates, and a method of driving the same.
A known type of non-volatile semiconductor device is a metal-oxide-nitride-oxide semiconductor or substrate (MONOS), wherein a gate insulating layer between the channel and the gate is formed of a multi-layer stack of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and charge is trapped in the silicon nitride film.
This MONOS type of non-volatile semiconductor memory device was disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123. This document disclosed a MONOS flash memory cell provided with two non-volatile memory elements (MONOS memory elements or cells) controlled by one word gate and two control gates. In other words, each flash memory cell has two charge-trapping sites.
A plurality of MONOS flash memory cells of this configuration are arranged in both a row direction and a column direction, to form a memory cell array region.
Two bit lines, one word line, and two control gate lines are connected to this MONOS flash memory cell.
The operations of this type of flash memory include data erasing, data programming, and data reading. Programming and reading of data are generally performed in 8-bit or 16-bit selected cells (selected non-volatile memory elements) at the same time. Each bit signal is input or output through an I/O line.
Therefore, each of the bit lines connected with each of an appropriate number of memory cells is connected in common with one I/O line through one of a plurality of select gates. One bit line is connected with one I/O line through one of the select gates. Data is read or programmed in an 8-bit or 16-bit unit by performing this operation for eight or sixteen I/O lines at the same time.
A plurality of memory cells arranged in the row direction are divided into an appropriate number of block regions, and each block region corresponds to one I/O line.
Dummy cells having only one of first and second control gates and a word gate are disposed on opposite ends of each block region in a row direction.
Therefore, the number of dummy cells is increased as the number of block regions is increased. This gives rise to a problem in which an effective area of the memory cell array is decreased.
The present invention may provide a non-volatile semiconductor memory device which can be highly integrated by reducing the number of dummy cells, and a method of driving the same.
One aspect of the present invention provides a non-volatile semiconductor memory device comprising:
a memory cell array region in which are arranged a plurality of memory cells at least in a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates;
a plurality of bit lines extending in a column direction, each of the bit lines being connected to a connect line which connects a pair of memory cells adjacent to each other in the row direction;
a plurality of first select gates, each of which is connected to one of the bit lines; and
a plurality of I/O lines, each of which is provided for each 2N (N is an integer of 2 or more) first select gates and connected in common to 2N bit lines through 2N first select gates,
wherein the memory cell array region is divided into a plurality of block regions in the row direction corresponding to the I/O lines, each of the block regions including 2N memory cells in the row direction; and
wherein a second select gate is provided between one of the I/O lines corresponding to the i-th block region (i is an integer) and one of the bit lines, the bit line being located at a boundary between the block regions and connected to the connect line connecting two of the memory cells respectively disposed in the i-th and (i+1)th block regions that are adjacent to each other in the row direction in the block regions.
According to this aspect of the invention, the bit line located at the boundary between the i-th and (i+1)th block regions can be connected to the I/O line corresponding to the i-th block region with the interposed second select gate. This eliminates the need to provide a dummy cell between the block regions, whereby the degree of integration can be increased.
The second select gate may be driven on condition that the memory cell located in an end portion of the i-th block region and connected to one of the bit lines located at the boundary between the block regions is selected and that the bit line located at the boundary between the block regions is connected to one of the I/O lines corresponding to the i-th block region.
The bit line located at the boundary between the block regions may be set at a bit line voltage for programming through the second select gate when programming is performed for the second non-volatile memory element of the memory cell located in an end portion of the i-th block region.
Data reading from the first non-volatile memory element of the memory cell located at an end portion of the i-th block region may be performed in reverse mode by sensing a current flowing into the I/O line through the second select gate and the bit line located at the boundary between the block regions.
Data reading from the second non-volatile memory element of the memory cell located at an end portion of the i-th block region may be performed in forward mode by sensing a current flowing into the I/O line through the second select gate and the bit line located at the boundary between the block regions.
The memory cell array region may be divided into a plurality of sector regions in a row direction; and a plurality of independent control gate driver sections may be provided for each of the sector regions. In this case, each of the control gate driver sections can set the potential of the first and second control gates of the memory cells in a corresponding sector region independently of other sector regions. This prevents occurrence of disturbance in non-selected cells when programming or erasing data.
A dummy cell having one of the first and second control gates and the word gate may be disposed at both ends of each of the sector regions in a row direction. This is because when three memory cells are respectively disposed in adjacent two sectors, the first or second non-volatile memory element of the memory cell in one of the two sectors cannot be driven by using the three memory cells.
The bit lines respectively connected to the connect lines could be sub bit lines and the sub bit lines may be commonly connected to a main bit line extending in a column direction with bit line select switching elements interposed. In this case, the first and second select gates are connected to the main bit line.
Each of the first and second non-volatile memory elements may include an ONO film formed of an oxide film (O), a nitride film (N), and an oxide film (O) as a charge-trapping site, but other configuration could also be used.
According to another aspect of the present invention, there is provided a non-volatile semiconductor memory device which has: a memory cell array region in which are arranged a plurality of memory cells at least in a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates; a plurality of bit lines extending in a column direction, each of the bit lines being connected to a connect line which connects two of the memory cells adjacent to each other in the row direction; a word line which is connected to the word gates of the memory cells arranged in the row direction; and a plurality of control gate lines each of which is connected to the first and second control gates respectively provided in adjacent two memory cells with the connect line interposed, the memory cell array region being divided into a plurality of block regions in the row direction corresponding to the I/O lines, and each of the block regions including 2N memory cells.
In driving this non-volatile semiconductor memory device, a data reading or programming operation is performed for one of the first and second non-volatile memory elements in the i-th memory cell in the row direction by using the word line, four of the bit lines, and four of the control gate lines connected to the (ixe2x88x921)th, the i-th and the (i+1)th memory cells.
When the i-th memory cell is in an end portion of the block region, this operation is done by using the bit line and the control gate line connected to the (i+1)th memory cell in the block region which is different from the block region in which the i-th memory cell is located.
According to this aspect of the present invention, when three memory cells are respectively disposed in adjacent block regions, the data reading or programming operation can be performed for the first or second non-volatile memory element of one memory cell located at the center of the three memory cells in a row direction by using the three memory cells. Since dummy cells are not present at the boundary between two adjacent block regions, such operation can be achieved.
In this case, the memory cell array region may be divided into a plurality of sector regions in a row direction, each of the sector regions having a plurality of the block regions. In each of the sector regions, a data reading or programming operation can be performed by using the word line, four of the bit lines, and four of the control gate lines connected to the (ixe2x88x921)th, the i-th and the (i+1)th memory cells respectively disposed in adjacent two block regions. In other words, the memory cells respectively disposed in different sector regions will not be driven at the same time.
In this aspect of the present invention, a dummy cell having one of the first and second control gates and the word gate may be disposed at both ends of each of the sector regions in a row direction; and a data reading or programming operation may be performed for the i-th memory cell by using the bit line and the control gate line connected to the (ixe2x88x921)th or (i+1)th dummy cell, when the i-th memory cell is in an end portion of the sector region.